Nexperia offers engineers access to one of the most extensive CFP packaged diodes portfolios on the market from one supplier.

Nexperia will demonstrate how its ongoing commitment to investment in R&D and capacity is supporting these megatrends with its expanding portfolio

The expansion of Nexperia’s expertise comes through the acquisition of Netherlands-based Nowi, founded in 2016.

Since the launch of ASFETs, success has been seen with products optimized for battery isolation, DC motor control, Power-over-Ethernet, automotive airbag applications and

Standard products include the PNU65010ER (CFP3) and PNU65010EP (CFP5) while AEC-Q101 qualified products include the PNU65010ER-Q (CFP3) and PNU65010EP-Q (CFP5).

Nexperia developed the TrEOS portfolio specifically to offer our customers a range of high-performance ESD protection solutions for applications such as USB3.2, USB4™, Th

In contrast to the battery voltage found in cars and smaller vehicles, 24 V board nets are typically used in trucks and commercial vehicles.

Nexperia developed the X2SON packages - part of its MicroPak package range - to provide the smallest footprint for logic functions while ensuring pad pitch remains 0.4mm

With a maximum RDS(on) of 0.67 mΩ, Nexperia’s PSMNR58-30YLH MOSFET improves the maximum drain current rating up to 380 amps.

Developed to meet the requirements of Super Speed USB applications, the new devices provide effective 1, 2 & 3 line pair protection (Tx +/-, Rx +/-, D +/-) and filtering.

Nexperia’s GaN-on-silicon process is very robust and mature with proven quality and reliability, plus it is highly scalable as wafers can be processed in existing silicon

Nexperia’s TrEOS technology optimizes the three pillars of ESD protection to deliver devices with the ideal combination of low capacitance, low clamping voltage and high

Measuring just 2 mm x 2 mm (14 pin), 2 mm x 2.4 mm (16 pin), 2 mm x 3.2 mm (20 pin) and 2 mm x 4 mm (24 pin), the 0.4 mm pitch DHXQFN packages are only 0.45 mm high.

These products use Nexperia’s proven TrEOS technology, which combines low clamping with low capacitance and high robustness.

This development results in the increasing need for voltage translators to connect the SoC to other standard process devices and I/O ports like legacy Class B and Class C